1. Field of the Invention
A semiconductor device constituted by MOS transistors is applied in diverse fields such as home electric appliances, AV equipment, information equipment, communication equipment and automobile electric equipment. In recent years, the need for power management ICs having the function of being able to supply a stable power source such as a voltage regulator, a switching regulator or a charge pump regulator, a voltage monitoring function such as a voltage detector or battery protection, or an over-current monitoring function has increased along with the portability of electrical machinery and devices. The present invention relates to a semiconductor device which has the power source supplying function and the power source monitoring function as described above.
2. Description of the Related Art
In MOS transistors for use in semiconductor devices, normally, there are used contacts each having a contact size of a minimum value of the process limit of normal contacts, or a minimum value of the process rule for manufacture of the MOS transistors. The maximum amount of current allowed to flow by one contact normally depends on the contact size. Therefore, with respect to the size of a contact of a MOS transistor connected between terminals of a semiconductor device for the purpose of protecting a MOS transistor used in an output stage requiring a large current or an internal circuit of a semiconductor device from the electrostatic breakdown, although a contact having a size larger than that of a minimum value of the process limit of contacts or a minimum value of the contact rule for manufacture of the MOS transistors may be employed in some cases, normally a contact is employed the sides of which have the same length.
FIG. 6 shows a MOS transistor connected between the terminals of the semiconductor device for the purpose of protecting a MOS transistor used in an output stage requiring a large current or an internal circuit of the semiconductor device from the electrostatic breakdown, and contacts of a source and contacts of a well are arranged close to each other in order to prevent the parasitic bipolar operation and the latch-up. Furthermore, in the case where it is strongly required to prevent the parasitic bipolar operation and the latch-up, contacts of a source and contacts of a well are made batting contacts in many cases.
In the case where contacts of a source and contacts of a well are made batting contacts, conventionally, the batting contacts are formed as shown in the arrangement of FIG. 6.
Numeral 1 is a PMOS region, 2 is an N-type diffusion region, 3 is an N-type well, 4 is a gate, 5 is a drain, 6 is a source, 7 is a gate wiring, 8 is a drain wiring, 9 is a source or well wiring, 11 is a gate contact, 12 is a drain contact, 13 is a source contact, and 14 is a well contact.
However, some MOS transistors which are each connected between terminals of a semiconductor device for the purpose of protecting a MOS transistor used in an output stage requiring a large current or an internal circuit of a semiconductor device from the electrostatic breakdown, have a transistor width ranging from several hundreds of xcexcm to several tens of mm, which is large in size. Each of these MOS transistors used generally has a shape in which a plurality of gates are arranged in parallel with one another. For this reason, in MOS transistors each having a large transistor width, the interval of the adjacent gates influences greatly on the transistor size.
While the interval of the adjacent gates in a drain is determined by a distance between a gate and a contact, and a contact size, the interval of the adjacent gates in a source is determined by a distance between a gate and a contact, a contact size and a width of a diffusion region, having the same polarity as that of a well, for obtaining the well contact.
In the above-mentioned power management IC, for the purpose of preventing a MOS transistor used in a output stage, or an internal circuit of a semiconductor device from the electrostatic breakdown, the rate of occupation of the MOS transistor connected between the terminals of the semiconductor device in a chip is large. Therefore, a MOS transistor is desired which has a contact shape of a drain, a source or a well allowing a larger current to flow with a smaller gate interval, and a batting contact shape allowing a smaller gate interval.
In the light of the foregoing, the present invention solves the above-mentioned problems by employing a contact between each portion of a MOS transistor and metallic wiring, the contact having one arbitrary side that is longer than the other side in a semiconductor device constituted by MOS transistors.
That is, with respect to a shape of the contact, an arbitrary one side of the contact is made longer than the other side, and the longer side of the contact is formed in parallel with a transistor width (or channel width) direction of the MOS transistor, whereby it is possible to lengthen a side not contributing to the interval of the adjacent gates while maintaining a side contributing to the interval of the adjacent gates short. As a result, it is possible to increase the area of the contact to increase further a current caused to flow through the contact.
At this time, the length of the shorter side of the contact is made a minimum value of a contact rule for manufacture of the MOS transistor, whereby it is possible to minimize the interval of the adjacent gates.
In addition, in a MOS transistor in which contacts of a source and contacts of a well of the above-mentioned MOS transistor are made batting contacts, an arbitrary one side of a diffusion region having the same polarity as that of a well of a well contact portion of the batting contact is shorter than the other side, the one side shorter than the other side of the diffusion region having the same polarity as that of the well is formed in a transistor width direction, and the length of the batting contact in a gate length direction is made shorter than the length of the diffusion region having the same polarity as that of the well in a gate length direction. Thus, the present invention intends to solve the above-mentioned problems associated with the prior art.
An amount of overlapping between the batting contact and the diffusion region having the same polarity as that of the well in the gate length direction may be made a minimum value having the margin estimated from the process accuracy of the batting contact, and the alignment accuracy between the batting contacts and the diffusion region.
At this time, with respect to the shape of the batting contact, an arbitrary one side of the contact is longer than the other side, and the one side longer than the other side of the contact is formed in a transistor width direction, whereby it is possible to further shorten the interval of the adjacent gates. In addition, the length of the shorter side of the contact is made a minimum value of the process limit of contacts, or a minimum value of a contact rule for manufacture of the above-mentioned MOS transistor, whereby it is possible to minimize the interval of the adjacent gates.
The contact or the batting contact having the shape as described above may be applied to only a contact requiring a large current, and may be applied to a contact with a drain, a source or a substrate of a MOS transistor connected between the terminals of the semiconductor device for the purpose of protecting a MOS transistor used in an output stage or an internal circuit of the semiconductor device from the electrostatic breakdown. Also, a contact of a MOS transistor used in an internal circuit may be a square contact one side of which is made a minimum value of the process limit of contacts, or a minimum value of the process rule for manufacture of the MOS transistor. At this time, the length of the shorter side of the contact having the above-mentioned shape, if there is no problem for the process of the contacts, maybe shorter than a side of a contact of a MOS transistor used in an internal circuit.
In addition, the contacts each having the above-mentioned shape or the batting contacts may be arranged at contact intervals of a minimum value of the process limit of contacts or a minimum value of the process rule for manufacture of the MOS transistor within a transistor width of the MOS transistor connected between the terminals of the semiconductor device for the purpose of protecting a MOS transistor used in an output stage or an internal circuit of the semiconductor device from the electrostatic breakdown, as much as possible.